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triple half-bridge dmos output driver with serial input and pwm control ata6831/ata6832 1. introduction ata6831 and ata6832 are fully protected uni versal driver interfaces designed in smartis1 technology. they are used to control up to 3 different loads by a microcon- troller in automotive and industrial applications. the ata6831 is housed in a qfn18 4 4 mm package. each of the 3 high-side and 3 low-side drivers is capable of driving currents of up to 1a. the drivers are internally connected to form 3 half-bridges and can be controlled separately from a standard serial peripheral data interface. therefore, all kinds of loads such as bulbs, resistors, capacitors, and inductors can be combined. the ic design particularly supports the application of h-bridges to drive dc motors. the pwm feature allows a smooth operation of dc motors and bldc motor control. pro- tection against short-circuit conditi ons, overtemperature, and undervoltage is implemented. various diagnosis functions and a very low quiescent current in standby mode open a wide range of applications. automotive qualification referring to con- ducted interferences, emc, and 2 kv esd protection gives added value and enhanced quality for demanding up-market applications. ata6831 is designed to operate on junction temperatures up to 150c. ata6832 is designed for high temperature applications on junction temperatures up to 200c if not explicit mentioned, all comments in this document for ata6831 are valid for ata6832 as well. ata6831/ ata6832 driver ics application note 9120a?auto?01/08
2 9120a?auto?01/08 ata6831/ata6832 driver ics figure 1-1. triple half-bridge dmos output driver with serial input control ata6831
3 9120a?auto?01/08 ata6831/ata6832 driver ics 2. design kit the design kit includes the following components: application board ata6831-dk design software link cable to pc 25-lead 1:1 application note datasheet ata6831 and ata6832 3. description the core of the ata6831-dk design kit is a pc -controlled application board. using the ata6831 design kit, users can easily ad apt their loads via row connector pins (refer to ata6831). the design software interface controls the design ki t. the pwm input clamp allows to modulate the pace signal. 4. features screwless row connector pins for external loads switched by low-side or high-side drivers easy and direct adaptation of loads with the ata6831 design kit direct switching of loads to v s or gnd fully driver function for v batt up to 40v forward/reverse rotation of dc motors by full-bridge application paralleling of outputs for powerful applications pc linked via standard ?sub-d? con nectors (plug x2 in ata6831-dk) input for 5v vcc power supply on board or externally using row connector 2 input pin pwm on row connector 2 indication of rotation direction of dc motors by leds, best function at v batt = 12v pc-controlled functions via software user interface all pins are easily accessible via test points
4 9120a?auto?01/08 ata6831/ata6832 driver ics figure 4-1. ata6831-dk application board schematic v s1 v s2 v cc v cc v s v s v cc 1 2 3 4 5 6 7 8 9 10 22 21 20 19 18 17 16 15 14 13 12 11 25 24 23 r2 pwm out3 out2 out3 6 1 2 12 13 15 16 do 7 cs 3 clk 5 di 4 r3 r4 r5 s3 mb12 r8 3.3 k ? r6 gnd vbatt 13v (6 to 40v) r1 d2 vcc 200 ? c3 c4 100 nf 10 f c1 c2 u3 lm2936 s1 s2 10 k ? 10 k ? 10 k ? 1 k ? 10 k ? byv28 d1 serial interface input register output register h s 3 l pp s 3 h s 2 l s 2 h s 1 l s 1 s s r o op p pp l d l hlh h l p s f i n h o v l n. u. h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 t p c s i n. n. n. n. n. s332211 out1 out2 out3 x1 row connector 1 gnd pwm gnd row connector 2 x2 detect fault detect fault detect fault detect fault detect fault detect fault control logic charge logic ata6831 ata6832 uv protection thermal protection power-on reset 11 10 gnd 100 nf 100 f 8 gnd 14 gnd 17 gnd mb12 mb32 mb21 d7a d4 d3 d7b 18 9 s4 mb23 r9 3.3 k ? mb23 d8a d6 d5 d8b
5 9120a?auto?01/08 ata6831/ata6832 driver ics figure 4-2. ata6831-dk design kit, application board component placement; top side, top view figure 4-3. ata6831-dk design kit, application board top side, top view
6 9120a?auto?01/08 ata6831/ata6832 driver ics figure 4-4. ata6831-dk design kit, application boar d; bottom side, top view (as if pcb were transparent)
7 9120a?auto?01/08 ata6831/ata6832 driver ics 5. design software 5.1 installation the ata6831 design kit includes the software ata6831. the user can also download the latest revision of the software from the atmel ? web site, http://www.atmel.c om/. start the installation process by running the .exe file from the cd-rom or from the downloaded file. the ata6831.exe file is saved to a user-defined directory (for example, d:\programs\ata6831), and the system files are saved to the system director ies. use the parallel cable supplied with the kit to connect the pc?s parallel port to the basic application board. double-click the ata6831 icon to start the software user interface ( figure 5-1 ). figure 5-1. software icon 5.2 description the ata6831 design kit and the software user in terface demonstrate the principal functions of the ata6831 and enable designers to create a design according to their own requirements. the software user interface includes all functions of the ata6831 and provides convenient control of the ata6831 via the application board. use the adjust register (representing the microcontroller) on the left side of the software user interface to pre-adjust the required input data ( figure 5-2 on page 8 ). selecting phx or plx will switch the output stage to pwm mode; in this case an exter- nal pwm signal with 5v coms logic level and maximum frequency up to 25 khz has to be applied to the board. any output set to pwm mode is tagged with a dedicated pwm symbol in the software user interface. click the send data button to shift the pre-adjusted data (16 bits) into the input register of the serial peripheral in terface. the output drivers are activated in accor- dance with the 16-bit input information. for more detailed information about the serial peripheral interface, please refer to the datasheet for ata6831. click the send data loop button to initiate an uninterrupted data tr ansfer. in this case, each out- put is directly adjusted by switching the accessory bit. click the reset button to reset all bits to the starting condition. click the end button to switch the software off. by default, 3 input register bits are selected, setting the bits to ?1? and choosing the following modes: si = software inhibit is set, for normal operation ocs = overcurrent shutdown is set, activating overcurrent shutdown old = open-load detection is set, turning open-load detection off before the first data word is sent, the ic is in standby (inhibit) mode. as soon as the first data word is sent, the ic reports the previous condition. if available, up to three parallel interface ports (lpt1 to lpt3) can be selected to establish a connection. the software detects the connected port.
8 9120a?auto?01/08 ata6831/ata6832 driver ics 5.3 ordering information please contact your atmel sales office or distributor. figure 5-2. software user interface
9 9120a?auto?01/08 ata6831/ata6832 driver ics table 5-1. functions of the serial interface register bits bit input register function 0 srr status register reset (hig h = reset; the bits psf, opl, and scd in the output data register are set to low) 1 ls1 controls output ls1 (high = switch output ls1 on) 2 hs1 controls output hs1 (high = switch output hs1 on) 3 ls2 see ls1 4 hs2 see hs1 5 ls3 see ls1 6 hs3 see hs1 7 pl1 output ls1 additonally controlled by pwm input pin 8 ph1 output hs1 additonally controlled by pwm input pin 9 pl2 see pl1 10 ph2 see ph1 11 pl3 see pl2 12 ph3 see ph2 13 old open load detection (low = open load currents are active) 14 ocs overcurrent shutdown (high = overcurrent shutdown is active) 15 si software inhibit; low = standby, high = normal operation (data transfer is not affected by the standby function because t he digital part is still powered)
10 9120a?auto?01/08 ata6831/ata6832 driver ics 6. applications 6.1 demonstration application a typical demonstration application consists of a dual full bridge arrangement with microcontrol- ler and watchdog to control two dc motors. such dual h-bridge arrangement with common mid-rail allows independent control of the motors for both rotation directions. enter the appropri- ate dataword according to table 6-1 on page 11 to set the required function. instead of hsx and lsx, the corresponding bits phx and plx can be used to control the motor speed by an external pwm signal. when operating in a safety-critical environment, the use of a separate watchdog ic is recom- mended (for example u5021m). if old is activated, the open-load detection is active for all outputs stages that are currently switched off. a pull-up current for each high- side switch and a pull-down current for each low-side switch is turned on (open-load detection current ihs1-3, ils1-3). if vvs-vhs1-3 or vls1-3 is lower than the open load detection threshold, an open-load is detected: in the output register the corresponding bit of the appropriate output is set to high. if no outputs were activated, all low-side drivers of half bridges are detected as open loads. this behavior is caused by the low-side open-load-detection current being larger than its high-side counterpart. this configuration ensures that with half-bridge or h-bridge applications the open-load detection also works in a well-defined way. if, for example, an open load at motor m1 should be detected, hs1 or hs2 has to be switched ?on?, while the diametrical low-side output register ls2 and ls1 respectively has to be evaluated. if inh is activated by software inhibit bit si, all activated loads are switched off, but the input and output registers remain set. short-circuit detection can easily be demonstrated by intentional false activation of the half-bridge components, for example, hs1 and ls1. this causes the ovl bit in the output regis- ter to be set. depending on the ocs bit, the affected outputs are switched off either by reaching overtemperature or by reaching overcurrent. the co rresponding status bits in the output register are set to low. the ovl bit can be reset, and th e disabled outputs can be re-enabled by activat- ing the srr bit. please note that such activa tion of srr only initiates a reset pulse, not a permanent reset state. the overtemperature prewarning is visible at the tp bit. when the cs pin is set to low, the pre- warning information is visible in real time at the do pin because tp is the first bit of output register. consequently, the tp bit is not buffered. in case of overtemperature shutdown only overheated output switches off. the other outputs are not touched. the dedicated output cannot be switched on again until activating the srr bit. as all high-side drivers are internally connected to their low-side counterparts in order to form a half-bridge, switching from hs active to ls active or vice versa with a single programming sequence could potentially imply some shoot-t hrough current peak across both drivers during the switching operation. the intelligent internal timing of ata6831 guarantees that such cross- over currents are avoided.
11 9120a?auto?01/08 ata6831/ata6832 driver ics undervoltage detection can be demonstrated with a variable power supply. as soon as the sup- ply voltage vvs falls below threshol d, all activated loads are switc hed off, and the psf bit in the output register is set. if the voltage returns to the normal level, the outputs switch on again to their previous setting. the psf bit latches the undervoltage occurrence and needs to be reset by srr activation in the input register. if the ic is not used in the typical h-bridge arrangement, parallel operation of outputs is possible for more powerful applications. two output stages at a time can be paralleled to achieve cur- rents up to 2a. in any case, the ic's maximum power dissipati on has to be considered. excellent thermal con- tact to an on-board cooling area is obligatory for powerful applications. note: x = do not care for this demonstration; if set to high: overcurr ent shutdown is active table 6-1. configuration table of datawords required to set certain functions of the appli- cation circuit (see figure 6-1 on page 12 ) bit 13 (ocs) bit 6 (hs3) bit 5 (ls3) bit 4 (hs2) bit 3 (ls2) bit 2 (hs1) bit 1 (ls1) bit 0 (srr) m1 forward xhh m1 reverse xhh m2 forward xh h m2 reverse xhh
12 9120a?auto?01/08 ata6831/ata6832 driver ics figure 6-1. application with microcontroller and watchdog v cc v cc v cc v cc 5v v batt v s v s 13v byw32 serial peripheral interface input register output register h s 3 l s 3 h s 2 l s 2 h s 1 l s 1 n. u. h s 3 t p i n h p s f o c s s r r o v l l s 3 h s 2 l s 2 h s 1 l s 1 s i n. u. n. u. n. u. n. u. n. u. detect fault detect fault detect fault detect fault detect fault detect fault control logic u5021m watchdog charge pump uv protection thermal protection power-on reset 5 gnd 26 gnd 13 v cc 19 microcontroller gnd 29 gnd 31 out1 out2 trigger reset out3 m1 m2 pwm 11 do 17 cs 6 clk 10 di 7 3 22 28 v s 21 o l d p h 3 p l 3 p h 2 p l 2 p h 1 p l 1
13 9120a?auto?01/08 ata6831/ata6832 driver ics 6.2 parallel operation of several ata6831s in applications with a high number of loads, parallel operation of the ata6831 via the microcon- troller is possible. chip select pins cs1 to cs4 ea ch provides an independent me ans of controlling the ata6831?s serial peripheral interface. (for a functional desc ription of the serial per ipheral interface, please refer to the datasheet.) for simultaneous operation of the serial peripher al interfaces (i.e., cs1 through cs4 active at the same time), each of the data outputs (do) needs to communicate with a dedicated micro- controller input pin. figure 6-2. parallel operation with microcontroller and watchdog 6.3 daisy chaining of several ata6831s daisy chaining is a second option available to connect several ata6831s to the microcontroller for applications with a high number of loads. a daisy chain arrangement requires only one cs line. the data signal is handed over step-by-step from one ata6831 to the next as long as cs signal stays low. the use of only one cs link, ho wever, results in slower reaction times, as sev- eral programming cycles are needed to load the desired setting into each ata6831. the di pin of the first ic acts as input for all ics, and the do of the last ic represents the output for the whole chain. the dataword intended for the la st ic has to be put in first, followed by the word for the ic before and so on. in contrast to other ics of the atmel driver family, only a total of n shifts are needed for n ics as any di information is transferred immediately to the output register. v cc v cc reset trigger enable cs1 clk do di inh ata6831 ata6831 ata6831 cs clk do di cs clk do di cs clk do di inh inh inh cs2 cs3 cs4 cs clk do di ata6831 u5021m watchdog micro- controller
14 9120a?auto?01/08 ata6831/ata6832 driver ics table 6-2 clarifies the daisy chain method. the n = 3 datawords a, b, and c shall be shifted into the driver ics 1, 2 and 3. the initial content of the registers are termed as x to z. the required status of the input registers di is reached after n = 3 shift operations. figure 6-3. daisy chain operation with microcontroller and watchdog v cc v cc reset trigger enable cs clk do di inh ata6831 ata6831 ata6831 micro- controller cs clk do di cs clk do di cs clk do di inh inh inh cs clk do di ata6831 u5021m watchdog table 6-2. principal method of shifting datawords through daisy-chained ics i/o cycle 0 1 2 ic number 123123123 di a b a c b a do zyxazybaz
15 9120a?auto?01/08 ata6831/ata6832 driver ics 6.4 driving a bldc motor with ata6831 the pwm capability of the ata6831 allows to run bldc motors, see figure 6-4 . for detailed information see application note http://www.atmel.com/dyn/resources/prod_documents/doc4987.pdf figure 6-4. bldc motor control application bldc motor ata6831 ata6625 atmega88 vcc regulator battery lin charge pump spi, pwm hall protection 16 bit spi, pwm diagnosis watchdog trx lin rx tx vcc speed control commutation + v w u
16 9120a?auto?01/08 ata6831/ata6832 driver ics 7. thermal considerations 7.1 cooling area design the ic should be connected to an on-board cooling area. all thermal pins (4 gnd pins) as well as the exposed die pad are directly adapted to the cooling area. figure 7-1 shows the cooling arrangement of the ata6831?s qfn 4 4 mm housing. the effect of the cooling area on the pcb can be further improved if the bottom side of the pcb is ground-plated and thermal vias are placed along the cooling area. some care should be taken of the copper area?s planarity, in particular, any solder bumps arising at the thermal vias should be avoided. figure 7-1. recommended cooling area extension and pcb pin layout ata6831 1 pcb top side cooling area pcb bottom side cooling area thermal vias
17 9120a?auto?01/08 ata6831/ata6832 driver ics 8. overload considerations 8.1 driver output shorted to v s during normal operation ata6831 is protected against short circuits by an overcurrent limitation. however, some attention has to be paid to certain abnormal operating conditions that might occur in practice. in particular, consider the case of an output shorted to v out while the ic is not connected to supply voltage v s . under these conditions, an unwanted backward current flows from the shorted output via the voltage supply pin to the capacitor c1. figure 8-1 illustrates this situation. the backward current i b flows from outx via the hsx output stage to the vs pin until the capac- itor c1 is charged to v out (minus drop across the diode). its value is strongly influenced by the capacitance of c1, but the quality of c1 (esr) and any parasitic resistance can also have an impact. the recommended range of c1 is 22 f to 100 f. as stated in the ata6831 datasheet, the maximum reverse current is 17a for a du ration of 150 s. the graph illustrated in figure 8-2 shows the typical voltage and reverse current gradients for a capacitor value of 100 f. figure 8-1. current flow in case of outx shorted to v out figure 8-2. current and voltage gradients for v out = 16v, c1 = 100 f; channel 1 = i b , channel 2 = v vs , channel 3 = v out v ou t v s c1 ata6831 hsx outx i b
18 9120a?auto?01/08 ata6831/ata6832 driver ics 8.2 inductive shutdown a driver ic faces a challenge when an inductive load is connected to its outputs as the energy stored in the inductance leads to a voltage peak when the load is switched off. an inductive load connected to the low-side driver outputs causes a voltage peak with positive polarity, while for the high-side outputs such peak is negative. in order to prevent any damage to the ic's output stages, some protective measures have to be implemented. figure 8-3 illustrates the principle protection circuit of the outputs. figure 8-3. principle clamping structure at a driver stage the clamping structures at the output stages limit the voltage peak and provide a path for the current after switching off. the maximum inductive shutdown energy for ata6831 is specified as 15 mj. this value applies for both low-side and high-side outputs. the energy, wl, stored in the inductor l during the switched-on state can be calculated using the following formula: outy ata6831 vs outx w l li l 2 2 -------------- - =
19 9120a?auto?01/08 ata6831/ata6832 driver ics figure 8-4. inductive pulse at low-side output; channel 1: gradient of v out [10v offset], channel 2: gradient of i out [200 ma/div.], pulse energy: w l = 10 mj. 8.3 discharger circuit many applications use an inverse-polarity protection diode, such as d1 in figure 8-5 , in the power supply feed to prevent any damage if v s is applied with the wrong polarity. despite the popularity of this method, it involves a risk of damage. during inhibit mode, the ic consumes only an extremely low current ivs, such as 5 a at maxi- mum. any peaks on the supply voltage (v pk in figure 8-5 ) gradually charge the blocking capacitor (c9 in figure 8-5 ). d1 prevents the capacitor from discharging via the power supply. because of the extremely small quiescent current, discharging via the ic can also be neglected. this means that during long periods in inhibit mode, the ic?s supply voltage could increase con- tinuously until the maximum supply voltage limit of 40v is exceeded, damaging the ic. ata6831, therefore, features a discharger circuit that prevents such unwanted effects. if v s exceeds a threshold value of approximately 27v , the blocking capacitor is discharged via an integrated resistor until v s falls again below the threshold. figure 8-5. functional principle of the discharger circuit ata6831 vs v p k v batt c9 d1 2 k ? 26.8v
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